Talent, not design software, is the biggest bill for chip startups: Cadence's Jayashankar Narayanankutty

Semiconductor startups in India face a challenge in finding people who can design, verify and take a chip through fabrication and into a commercial product, according to Cadence Design Systems group director Jayashankar Narayanankutty. This challenge is bigger than the cost associated with electronic design automation (EDA) licences needed to build a chip.

“If you ask me, the biggest line item in your business plan is always people. That is the most expensive,” Narayanankutty told ET AI during SEMICON India 2026.

His comments come at a time when India looks to turn its large design workforce into companies that own intellectual property and sell chips globally, instead of providing engineering services. While EDA tools can be expensive, Narayanankutty said the cost should not be treated as an entry barrier for startups.


“I am not saying EDA is cheaper, but there are ways to make it accessible,” he said.

Cadence has been working with startups on licensing models that take into account their limited cash flows, deferring revenue until they begin generating income or raise external funding, he said. Once a proof of concept is ready, startups typically buy their own tools and host them on their servers or Cadence’s cloud infrastructure, he added.

“The tools are in range with your manpower costs,” Narayanankutty elaborated. “It’s not very different on a per seat basis if you think. On a yearly basis, what you would spend for an engineer, a good engineer, is what you would spend for the tools also.”

The bigger gap is in trained and experienced people, he said. India needs more engineers across the semiconductor ecosystem, including design and manufacturing, but it also lacks senior talent that can take chips from design to a finished product.

“Our shortage is definitely trained manpower across the board,” he said. “At the senior levels, we do have a considerable gap in the knowledge of taking something to product [level].”

The gap extends beyond designing a chip and making it work. Engineers also need experience in fabrication, packaging, testing, identifying customers and taking a product to the market, he said. The entry-level shortage is a question of volume, while the senior-level gap is about specific product expertise.

The government’s Design Linked Incentive (DLI) programme has helped create a base for this ecosystem. The number of companies in the programme has increased from zero to 105 in about four years, he said. Around 20 have received external funding, while at least 80 have received their first fabricated chips or are close to tape-out and fabrication, Narayanankutty added.

However, startups will need support in accessing fabs and managing supply chains as they move towards commercial production. A typical startup may have only five people with strong engineering skills, but little experience in negotiating manufacturing arrangements, Narayanankutty said.

“You have so many tape-outs and products under your belt. But you have never gone and negotiated a supply chain,” he said.

This is where India may need an industry-level mechanism to aggregate access to fabs in Taiwan, Korea and other locations. Small companies may not have the scale or expertise to negotiate with global foundries on their own, Narayanankutty explained.

AI tools could help engineers manage the growing complexity of chip design, but they will not remove the need for experienced people, he added.

“If you take the same engineer, if he had to do one solution today, in the new world, he will have to solve 10,” he said. “It is not necessarily compressing the time. It is actually doing a lot more within the same time,” he added.